CON

  _clkmode = xtal1 + pll16x
  _xinfreq = 5_000_000

  IR_EMITTER_PIN  = 0
  LCD_PIN         = 23
  SW_UP           = 19
  SW_DN           = 17
  SW_LF           = 20
  SW_RT           = 18
  SW_CN           = 16

  low             = 850
  high            = 2050
  
  
var

  long ud, lr

obj

  dbg   : "Parallax Serial Terminal"
  lcd   : "Debug_Lcd"
  js    : "RCTIME"
  
pub go

  'dbg.start(115_200)
  lcd.init(LCD_PIN, 19_200, 2)

  dira[IR_EMITTER_PIN]~~

  dira[SW_CN..SW_LF]~

  lcd.backlight(1)
  lcd.str(string("started"))

  freq(0, IR_EMITTER_PIN, 38_000)

  dira[0]~~
  ir_off
  repeat
    'ir_pulse(low)
    'ir_pulse(low)
    'ir_pulse(low)
    
    'ir_pulse(high)
    'ir_pulse(high)
    'ir_pulse(high)

    'fwd  0001_1000_0111_1111
    '     1111_1110_0001_1000

    send_code($01F8, 16)

    '01f8  0000_0001_1111_1000
    '      0001_1111_1000_0000
    
    pause(50_000)
    

pub send_code(code, bits)

  'code >>= 1
  
  repeat bits
    if (code & 1)
      ir_pulse(high)
    else
      ir_pulse(low)

    code >>= 1


pub ir_pulse(len)

  ir_on
  pause(381)
  ir_off
  pause(len)
  
  


pub ir_on

  outa[IR_EMITTER_PIN]~

pub ir_off
  outa[IR_EMITTER_PIN]~~



pri Pause(duration)

  'This function pauses program execution for approximately [duration] micro seconds
  'so 1_000_000 would be approximately one second.  Doesnt account for instruction
  'execution time overhead.

  if duration < 381
    duration := 381             'lower bound limit. anything lower than this, we
                                'have to wait until the counter comes back around,
                                'which is MUCH longer than [duration].
  waitcnt(((clkfreq / 1_000_000) * duration) + cnt)                                


PUB Freq(Module, Pin, Frequency) | s, d, ctr

'' Determine CTR settings for synthesis of 0..128 MHz in 1 Hz steps
''
'' in:    Pin = pin to output frequency on
''        Freq = actual Hz to synthesize
''
'' out:   ctr and frq hold ctra/ctrb and frqa/frqb values
''
''   Uses NCO mode %00100 for 0..499_999 Hz
''   Uses PLL mode %00010 for 500_000..128_000_000 Hz
''

  Frequency := Frequency #> 0 <# 128_000_000     'limit frequency range
  
  if Frequency < 500_000               'if 0 to 499_999 Hz,
    ctr := constant(%00100 << 26)      '..set NCO mode
    s := 1                             '..shift = 1

  else                                 'if 500_000 to 128_000_000 Hz,
    ctr := constant(%00010 << 26)      '..set PLL mode
    d := >|((Frequency - 1) / 1_000_000)    'determine PLLDIV
    s := 4 - d                         'determine shift
    ctr |= d << 23                     'set PLLDIV
    
  spr[10 + module] := fraction(Frequency, CLKFREQ, s)    'Compute frqa/frqb value
  ctr |= Pin                           'set PINA to complete ctra/ctrb value
  spr[8 + module] := ctr

  dira[pin]~~

PRI fraction(a, b, shift) : f

  if shift > 0                         'if shift, pre-shift a or b left
    a <<= shift                        'to maintain significant bits while 
  if shift < 0                         'insuring proper result
    b <<= -shift
 
  repeat 32                            'perform long division of a/b
    f <<= 1
    if a => b
      a -= b
      f++           
    a <<= 1